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News
Cypress’ HyperBus™ Memory Interface for Instant-on Applications Incorporated into JEDEC xSPI Electrical Interface Standard
2017-12-05 | ReturnCypress was the first NOR flash memory supplier to identify the market requirement for a high-speed, 8-bit bus and introduced the HyperBus interface in 2014, ushering in a new class of high-performance NOR flash and RAM solutions that enable instant-on functionality for autonomous driving and industry 4.0 applications. Cypress’ HyperBus-based memories include high-density HyperFlash™ NOR Flash devices with the bandwidth required for the highest-performance embedded systems and high-speed HyperRAM™ self-refresh Dynamic RAM (DRAM) devices for systems requiring expanded scratchpad memory. More information on Cypress’ HyperBus interface and industry-leading high-performance memory portfolio is available at http://www.cypress.com/products/hyperbus-memory.
“Cypress continues to be a driving member of the JEDEC working committee that developed and proposed the xSPI standard,” said Howard Sussman, a JEDEC Board of Directors Vice-Chairman. “For system integrators, the JEDEC standard provides the means to easily second-source xSPI-compliant Flash devices. Use of the standard provides a single PCB package footprint and enables a unified device driver for all xSPI memories that configures the memory system based on a standardized xSPI method.”
The xSPI standard defines requirements for the compatibility of high-performance x8 serial interfaces, including read and write commands, electrical characteristics, signaling protocols for command and data transfers, and a standard pin-out in a Ball Grid Array (BGA) footprint.
“We firmly believe an open industry standard from a recognized standardization body such as JEDEC is the best way to generate broad market support that benefits both customers and suppliers,” said Rainer Hoehler, Vice President of the Flash Business Unit at Cypress. “Having our HyperBus interface incorporated into the xSPI standard will make it easier for our customers to bring the convenience of instant-on to their systems.”
About Cypress HyperBus Interface
The efficient 12-pin Cypress HyperBus interface consists of an 8-pin address/data bus, a differential clock (2 signals), one chip select and a read data strobe for the controller, reducing the overall cost of a system. Memories based on the interface enable faster systems with quicker response times and rich user experiences. The HyperBus interface enables a wide range of high-performance applications, such as automotive instrument clusters, infotainment and navigation systems and factory automation systems.
Source:http://www.cypress.com/